Electronic digital computing machines



July 21, 1959 Filed March 23, 1954 A. ST. JOHNSTON ELECTRONIC DIGITALCOMPUTING MACHINES 17 Sheets-Sheet 1 1, 1959 A. ST. JOHNSTON 2,895,671

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ATTORNEYS July 21, 1959 A. $1". JOHNSTON 2,895,571

ELECTRONIC DIGITAL COMPUTING MACHINES Filed March 25, 1954 17Sheets-Sheet 17 WORD N9 H /4. W020 pemon n BEAT LL U TRACK N MI 2 3 4 56 7 8 910 n l2l3l4l5 l6l7 $192021 22252425 +8 mvzmoa ANDREW s1. JOHNSTONUnited States Patent ELECTRONIC DIGITAL COMPUTING MACHINES Andrew St.Johnston, Buntingford, England, assignor, by mesne assignments, toInternational Business Machines Corporation, New York, N .Y., acorporation of New York Application March 23, 1954, Serial No. 418,104Claims priority, application Great Britain March 24, 1953 6 Claims. (Cl.235--157) This invention relates to electronic digital computingmachines and is more particularly concerned with machines operating inthe serial mode with number and instruction words signalled as electricpulse trains. The invention is particularly, although by no meansexclusively, adapted to machines utilising word-length and otherregisters employing magneto-striction delay lines of the kind describedin the specification of copending USA. Patent Application Serial No.303,552, filed August 9, 1952, by R. Millership, now Patent No.2,790,160.

One object of the invention is to provide an improved control system forsuch machines which utilise instructions each containing a first and asecond storage address location defining signal and in accordancetherewith means are provided whereby the machine can be caused tooperate to utilise first said first storage address location definingsignal and subsequently said second storage address location definingsignal of each instruction or alternatively to utilise only said firststorage address location defining signal of such instruction.

In order that the invention may be more readily un derstood oneembodiment thereof will now be described with reference to theaccompanying drawings in which:

Figs. 1A, 1B and 1C form a composite block schematic diagram of theprincipal elements of an electronic computing machine embodying thepresent invention and show the signal and control interconnectionsbetween the various parts.

Figs. 2A, 3A and 4A show in symbolic form three different types ofstandard unit from which the machine is largely built 'up while Figs.2B, 3B, 3C, 4B, 4C are detailed circuit diagrams of different parts ofsuch units.

Fig. 5A shows the symbol used for a mixer device and Fig. 5B the circuitthereof.

Figs. 6A, 7A, 8A and 9A illustrate in symbolic form the units which makeup a word length register within the machine while Figs. 63, 7B, 8B and9B are detailed circuit diagrams of such units.

Fig. 10A shows the symbol and Fig. 10B the circuit details of anotherpart of the machine.

Figs. 11A, 11B, 11C, 11D, 11E, 11F and 11G show in block schematic formthe detailed arrangements of the different parts of the control unit ofthe machine.

Figs. 12A, 12B, 12C, 12D and 12F show in similar block schematic formthe arrangements of the different parts of the arithmetic unit of themachine.

Fig. 13 shows the reading and writing circuits of the machine, whileFig. 14 shows a number of electric waveform diagrams.

The machine to be described operates in the serial mode and in thebinary scale of notation with a digit signalling period of 3micro-seconds and a beat period of 102 micro-seconds to accommodate aword length of 32 digits plus a 2-digit period gap between adjacent beator word signalling times. As illustrated in Fig. 14, diagram (A), thefirst 32 digit periods 1, 2 32 of each beat constitute the active digitperiods and the remaining two periods, 33 and 34, the aforesaid gap.Unless otherwise stated, the active or operational potential level ofthe various electric pulse and other control waveforms is positive-going(usually approximately +8 v.) relative to a resting level which isnegative to earth (usually approximately 10 v.). Thus a gate circuit,for example, will be opened or made conductive when each of its variousoperative inputs is positive-going and will he closed or madenon-conductive when any one or more of such operative inputs is/are atnegative level.

Both numbers and instructions are signalled by similar 32-digit wordpulse trains wherein the binary value 1" is indicated by apositive-going pulse in any required digit period and the binary value0" by the absence of any such pulse from such period, the signalwaveform then remaining at its negative resting level. In number wordsignals the various signalling digit periods 1, 2 32 representprogressively increased binary powers such as 2, 2, 2 in the usual waybut in instruction words the various digit periods have the significanceindicated in Fig. 14, diagram (B) as follows:

Digits l-10, first address number (A1) Digits 11-13, control function(CF) Digits 14-16, transfer from accumulator (TFA) Digits 17l9,accumulator function (AF) Digits 20-22, transfer to accumulator (TIA)Digits 23-32, second address number (A2) Referring now to the blockschematic diagram of Figs. 1A, 1B and 1C, the machine includes a store Sfor holding both number and instruction words, a control system CL forreceiving signals including instruction words from the store S andproviding therefrom a series of appropriate timing and controlwaveforms, an arithmetic unit AU which includes a number of word storageregisters, a computing circuit and other ancillary parts for dealingwith number word signals supplied thereto and input and output devicesID, OD by which data may be fed into and withdrawn from the machine. Thelastmentioned input and output devices ID, OD can follow any of the nowwell known types by which input data can be supplied from perforatedtape through the intermediary of a tape reader and by which output datacan be derived by the operation of an electric typewriter: As theseparts are in no way concerned with the present invention they will notbe further described.

The store S comprises a magnitude disc or drum recording device MDproviding a plurality of separate tracks each having a plurality ofseparate word storage locations and a decoder circuit DCD for selectingany one of the available tracks for use either in reading out from orwriting into the store. This circuit DCD has a signal output lead 101for sup-plying word-representing pulse signal trains to unit DC of thecontrol system CL and to unit AG of the arithmetic unit AU. It also hasa signal input lead 102 by which word-representing signal pulse trainsderived from units ACCl, R, D and X of the arithmetic unit AU may berecorded in said recording device MD. Further output leads 103, 104supply re spectively a continuous timing signal and a series of addressindicating signals each occurring immediately prior to the period ofavailability of each word storage location. These signals are suppliedto unit PGA of the control system CL.

The control system CL comprises a pulse generator unit PGA which isdescribed in greater detail later with reference to Fig. 11A. This unitis supplied with the aforesaid timing and address signals from the storeS over leads 103, 104. The address signals are supplied therefrom, aftersuitable amplification and shaping, to a subsequent unit BC of thecontrol system over lead 105 and are also use l to provide a series ofdigit timing pulse waveforms 31, 31, 32, 32, 33, 33, 34, 34, l, 2, 3, 4,5, 6, 7, 8 and 9 Whose forms will be described in greater detail laterand which are made available throughout the machine by means of bus-barswhich are shown grouped together in a common multiple conductor supplycable GL1. The timing signals are used to derive a continuous series oftiming waveforms known as the Clock, Reset" and Strobe waveforms whichare also applied to all units of the machine.

The control system CL also includes a delay chain DC with which isassociated an instruction register ISR for retaining an appliedinstruction word signal until it has been obeyed. These units aredescribed in greater detail later with reference to Fig. 11B. The delaychain is supplied with output signals from the store S over lead 101 andalso with output signals from unit X of the arithmetic unit AU over lead107 and therefrom serves to provide a series of signal outputs, each atdifferent relative timings and referred to respectively as the PI 1, PI2, PI 13, PI 14, PI 15, PI 16, PI 17, PI 18, PI 19, PI 20, PI 21, PI 22and PI 23 waveforms. These PI 1 PI 23 waveforms are likewise madeavailable to units STR, BC, TSM and RWD of the control system overseparate bus-bars which are shown grouped together as a multipleconductor cable GL3.

The control system also includes a staticisor unit STR whose form willbe described in greater detail later with reference to Fig. 11C. Thisunit comprises four separate groups of staticisors, each group havingthree separate staticisor circuits, for dealing respectively with eachof the aforementioned three-digit groups CF, TFA, AF and TIA of aninstruction word. These staticisor groups are supplied with selectedones of the difference digit timing pulse waveforms in cable GL1 andwith selected ones of the delayed signal outputs of cable GL3 as well asa plurality of other controlling waveform inputs from other elements ofthe machine, as described later, and serve to provide four separategroups of function control waveforms whose character is dependent uponthe configuration of the related CF, TFA, AF and TTA digits of thecurrent instruction word supplied to the control system. These groups offunction co ntrol waveforms comprise the CF group of the i, 1:, k, l. lwaveforms, the TFA groups of the g, E, h, h, i, i waveforms, the AFgroup of the 61,3, 4 L7, waveforms and the 'ITA group of the a, a, b, F,c, F, waveforms. All of these waveforms are similarly made available tounits DC OS and RWD of the control system CL and units AG, COS, ACC1, R,D and X of the arithmetic unit AU by way of bus-bars shown as a multipleconductor cable GL2.

The control system CL further includes a beat circuit BC which will bedescribed in greater detail later with reference to Fig. 11D and whichincludes a coincidence testing circuit for comparing the address signalprovided over lead 105 from the pulse generator unit PGA with the firstaddress number signal A1 or the second address number signal A2 includedin an instruction and supplied from the outputs PI 2 and PI 14 from thedelay chain DC. Upon the existence of the required coincidence, thecircuit provides further control waveforms defining the variousoperative beats of the machine rhythm and including the z, 2, C, il c Band T3 waveforms. This beat circuit BC is supplied with a number ofdigit pulse timing waveforms from the cable GL1 and the TGB waveformfrom unit COS of the arithmetic unit AU as well as the Pl 2 and PI 14signals from the cable GL3 and receives also a control signal over lead106 from a further unit known as the single shot circuit OS whichprovides, upon the operation of suitable manual control keys, for theoperation of the machine to deal only with one single instructioninstead of the usual continuous and automatic operating rhythm. Thissingle shot circuit OS, which is described in greater detail later Withreference to Fig. 11E, is supplied with certain of the digit pulsetiming waveforms from the cable GL1, with certain function controlwaveforms from the cable GL2 and with the C and B waveforms from circuitBC as well as a further control potential over lead 108 derived from theinput or output units ID, OD.

The control system CL also comprises a further group of threestaticisors known as the track selection staticisors TSM and describedin greater detail later with reference to Fig. 11F. This group ofstaticisors is concerned with the selection of the required recordingtrack of the device MD and provides a further group of six trackselection waveforms m, :72, n51 0,; which are made available in thestore S over the multiple conductor cable GL4. This unit TSM is suppliedwith certain of the digit pulse timing waveforms in cable GL1 and withthe PI 1 and P1 23 signal waveforms in cable GL3 as well as the B and Bwaveforms from circuit BC.

The control system CL finally comprises a unit RWD described in greaterdetail later with reference to Fig. 11G and consisting of read/ writedecode circuits for providing output control waveforms R, and it whichare supplied ot the decoder circuit DCD of the store S for determiningWhether signals are to be read out from or are to be written into thedevice MD. This read/ write decode circuit RWD is supplied with certainof the digit pulse timing waveforms of cable GL1, with certain of thesignal waveforms of cable GL3 and with the B and pc control waveformsfrom circuit BC.

The arithmetic unit AU comprises an accumulator input gate unit AGdescribed in detail later with reference to Fig. 12F and by which anyrequired one of a number of alternative signal inputs may be routed to acommon output lead 110. The signal inputs available are those on lead111 from the input device ID, on lead 101 from the store S, on lead 107from a word register X of the arith metic unit, on lead 109 from anotherword register D of the arithmetic unit or on one or the other of leads113, 115 from a further word register R. This accumulator input gateunit AG is controlled by certain of the function control waveforms ofthe cable GL2.

The output on lead 110 from the accumulator input gate unit AG isapplied to a first word register ACC1 with which is associated acomputing circuit AS adapted to perform the functions of either additionor subtraction with, or the determination of non-equivalence between, afirst number representing signal held in the register ACC1 and a furthernumber representing signal applied thereto. This register also hasassociated therewith a first shift circuit SHl by which an output signaltrain may be derived in any one of three different relative timingsknown respectively as the Ac0, Acl and AC2 outputs. These elements willbe described in detail later with reference to Fig. 12A. A furtheroutput, having a timing identical with that of the Acl output, is fed tothe lead 102 connected to the further word registers R, D and X and thestore 5. The operation of this word register ACC1 is controlled by aselection of the function control waveforms of cable GL2, by certain ofthe digit pulse timing waveforms on cable GL1 and by a further controlwaveform 1 derived from the beat circuit BC of the control system CL.Directly associated with this word register ACC1 is a second wordregister ACCZ which can, effec tively, be included as part of the firstregister ACC1. by way of interconnecting leads 120, 121, 122 and 123.

The further word register R has associated therewith a second shiftcircuit SHZ by which an output word signal, at one or other of twodifferent timings, can be provided over the output leads 113 and 115leading to the accumulator gate unit AG. The signal input to thisregister is derived over lead 102 as already stated, The operation ofthis word register is controlled by a selection of the function controlwaveforms of the cable GL2, by a number of the digit pulse timingwaveforms in cable GL1 and by the z and z waveforms from beat circuit BCof the control system.

The further word registers D and X are generally similar to the registerR except that they are not provided with a shift circuit; each has asignal input from lead 102 as already stated and serves to providerespectively outputs over leads 109 and 107 to the accumulator gate unitAG. The control of each of these D and X registers is derived fromselected function control signals in cable GL2.

The arithmetic unit finally include-s a conditional order selector COSby which the further operation of the machine along a chosen one of twoalternative series of pro gramme steps can be made conditional upon atest operation effected upon a partial answer number which haspreviously been obtained. This conditional order selector COS issupplied with the differently timed output signals Ac0, A02 from theword register ACCl and with selected digit pulse timing and functioncontrol waveforms from the cables GL1 and GL2. In addition, it issupplied with the B waveform from beat circuit BC of the control systemCL and provides two further control waveforms,

known as the TC.B and TC.34 Waveforms, which are applied to the delaychain DC and the beat circuit BC respectively.

The machine is largely made up of a number of sep arate plug-in units ofthree types which are described in detail in U.S.A. patent specificationSerial No. 394,442, now abandoned. These three units are shownrespective ly in Figs. 2A, 3A and 4A and comprise, firstly a unitconsisting of two delay circuits each having a delay time of one digitperiod (hereafter called a unit delay), shown in Fig. 2A; secondly aunit consisting of a unit delay fed with the mixed or combined outputsfrom two multiple input coincidence gate circuits (hereafter called agate), and, separately, an inverter fed with the output from a gate,shown in Fig. 3A; and thirdly, a unit having three separate gates and atleast one separate cathode follower stage, shown in Fig. 4A.

Before dealing in greater detail with the construction and manner ofoperation of the various units of the store S, control system CL andarithmetic unit AU referred to above, a description will first be givenof a preferred form of each of the symbols used in the more detaileddrawing Figs. 11A, 11B, 11C, 11D, 11E, 11F, 11G, 12A, 12B, 12C, 12D, 12Band 13.

UNIT DELAY DEVICE Referring particularly to Fig. 2A, the symbol which isshown twice within the chain-dotted rectangle will hereafter be used toindicate a unit delay. Such unit delay has a single signal inputterminal 20 and two alternative signal output terminals 21, 22 both ofwhich provide similar output signals.

Fig. 2B shows the detailed circuit arrangement of such. unit delay. Thiscircuit comprises a pentode valve V200 which has its anode coupledthrough capacitor C201 to the control grid of a second pentode valveV201 by way of a closed loop containing, in series, an inductance L200,a capacitor C200 and two germanium rectifiers X200 and X201. Valve V201is arranged as a cathode follower. The signal input to the control gridof valve V200 is ap plied from input terminal 20 through resistor R200.Germanium crystal rectifier X202 is connected between the control gridof valve V200 and a bus-bar (not shown) carrying the Clock pulsewaveform which is shown in Fig. 14, diagram (C) and which is provided,as already stated. by the pulse generator unit PGA of the control systemCL (Fig. 18). Capacitor C200 and control grid of valve V201 areconnected through a pair of germanium rectifiers X203 to a furtherbus-bar (not shown) carrying the Reset pulse waveform which is shown inFig. 14, diagram (D) and 'which is also derived from said pulsegenerator unit PGA (Fig. 1B).

The control grid of valve V201 is also connected through resistor R202to source of negative potential 150 v. while the control grid of valveV200 is likewise connected to the same source through resistor R201. Thecathode of valve V201 is connected also to such source l50 v. throughresistor R203 and is additionally connected directly to output terminal21 and through blocking rectifier X205 to alternative output terminal22. Rectifier X204 connected between the cathode of valve V201 andsource of negative potential 10 v. acts as a clamp diode to prevent thecathode of that valve falling below -10 v. potential.

In the operation of this arrangement the arrival of a positive clockpulse at the control grid of valve V200 during the time when a positivesignal pulse is present through input terminal 20 produces a ring in theinductance L200. Whilst the valve is conducting a current builds up inthe inductance but as the resulting voltage across the latter isnegative-going, rectifiers X200, X201 prevent discharge of the capacitorC200. However, when the valve again ceases to conduct, at the end of thepositive clock pulse, the continuance of the current in the inductancemakes the voltages across the latter positive-going so that this currentthen charges capacitor C200 through rectifiers X200, X201.

The potential at the control grid of valve V201, which is normally helddown, accordingly rises to initiate a positive-going output pulse at itscathode. This output pulse persists until capacitor C200 is dischargedat the end of the next following clock pulse period by the appropriateReset pulse, Fig. 14, diagram (D), applied through rectifier X203. Itwill be appreciated that there was also a Reset pulse applied at thetime just after the valve V200 ceased to conduct, i.e. when the currentin the inductance L200 was about to charge the capacitor C200. However,this merely had the effect of deferring the initiation of the chargingof the capacitor until after such first Reset pulse had terminated, thecurrent in the inductance L200 flowing in the meantime through therectifiers X200, X201, and X203.

The voltage waveform appearing at the output terminals 21, 22 is shownin Fig. 14, diagram (F) relative to an input pulse train as shown inFig. 14, diagram (E).

Referring now to Fig. 3A, that part of the unit shown in symbolic formtherein lying at the left hand side comprises two coincidence gates GWhose respective outputs are combined and applied to a unit delay D.Fig. 3B shows the circuit of such a combined double gate and delay unit.The first gate G is of conventional form constituted by rectifiers X300,X301 and X302 connected by one terminal respectively to input terminals30, 31 and 32 and having their other terminals interconnected and joinedby way of resistor R301 to the positive sup ply source v. and also byway of rectifier X306 to the control grid of valve V200. The other gateG is similarly constituted by rcctifiers X303, X304 and X305 having oneof their terminals connected respectively to input terminals 33, 34 and35 and having their opposite terminals interconnected and joined by wayof resistor R302 to the positive supply source +100 v. Such commonconnection is also joined by way of rectifier X307 to the control gridof valve V200.

The unit delay is constituted by valves V200 and V201 and associatedparts in identical manner to that already described in connection withFig. 2B. In view of the identity similar reference numerals have beengiven and the unit delay will not be further described.

In the operation of such device, a positive-going potential must bepresent on each of the input terminals 30, 31 and 32 simultaneouslybefore any corresponding positive-going potential is applied to thecontrol grid of valve V200. Similarly a positive-potential must bepresent at each of the input terminals 33, 34 and 35 before anycorresponding positive potential is applied to the control grid of valveV200. A positive-going output from

